Integrated circuit bond pad structures and methods of making
US7232705B2 · kind B2 · utility
46Cited by
10References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 12, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Aug 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/601
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A bond pad structure for an integrated circuit includes first and second active devices formed in a substrate, first and second buses above the first and second active devices, respectively, a bond pad above the first and second buses, first interconnections between the first and second active devices and the bond pad, and second interconnections between the first and second active devices and the first and second buses, respectively. The first active device may be at least one PMOS transistor, and the second active device may be at least one NMOS transistor. A guard band region may be formed in the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.