Method and structure to prevent circuit network charging during fabrication of integrated circuits
US7232711B2 · kind B2 · utility
39Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | May 24, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit and method of fabricating the integrated circuit. The integrated circuit, including: one or more power distribution networks; one or more ground distribution networks; one or more data networks; and fuses temporarily and electrically connecting power, ground or data wires of the same or different networks together, the same or different networks selected from the group consisting of the one or more power distribution networks, the one or more ground distribution networks, the one or more data networks, and combinations thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.