Method of forming an integrated circuit incorporating higher voltage devices and low voltage devices therein
US7232733B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Dec 19, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A method of forming an integrated circuit configured to accommodate higher voltage and low voltage devices. In one embodiment, the method of forming the integrated circuit includes forming a transistor by forming a gate over a semiconductor substrate. The method of forming the transistor also includes forming a source/drain by forming a lightly doped region adjacent a channel region recessed into the semiconductor substrate and forming a heavily doped region adjacent the lightly doped region. The method of forming the transistor further includes forming an oppositely doped well under and within the channel region, and forming a doped region between the heavily doped region and the oppositely doped well. The doped region has a doping concentration profile less than a doping concentration profile of the heavily doped region. The method of forming the integrated circuit also includes forming a driver switch of a driver on the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.