High temperature and chemical resistant process for wafer thinning and backside processing
US7232770B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 3, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jul 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/2007
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process which uses a silicone resin to form a wafer-to-carrier bonded package that enables wafer thinning and backside processing while the cured resin exhibits high chemical and thermal resistance. The process is versatile in that the constructed wafer package allows for a wide range of chemical exposures to include dilute acid and base etchants, resist and residue strippers, electroplating chemistries, and also providing use in a range of deposition and etch processes that may exceed 300° C. The process utilizes a mixture of silicone monomers that when applied to semiconductor wafers by a spin-coat application, the result is a planarization of the front side device area, and when a subsequent thin coat is applied will facilitate bonding of the wafer-to-carrier package when heat and pressure are applied. The cured silicone bonded wafer-to-carrier package allows for wafer thinning consistent to industry objectives. Backside processing may include thermal oxide deposition, installed vias, and subsequent metallization in plating baths. Upon completion of a thinned and processed wafer, detachment occurs as described in prior art. Specialty chemical systems which completely dissolves…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.