CMOS input buffer and a method for supporting multiple I/O standards
US7233176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | May 16, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/08
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A CMOS input buffer supporting multiple I/O standards and having a pair of NMOS and PMOS differential receivers, each having a first input connected to an input pad and a second input connected to a reference voltage, a first multiplexer connected to the control terminal of the current sink of the NMOS differential receiver and having one input connected to the positive supply terminal, and a second multiplexer connected to the control terminal of the current source of the PMOS differential receiver and having one input connected to the negative supply terminal or ground. The buffer further includes an inverter connected to a combined output of the PMOS and NMOS differential receivers and having an output connected to the second input of the first and second multiplexer, and a configuration storage bit for selecting the desired inputs of the first and second multiplexer, thereby supporting high speed standards as well as general purpose standards while reducing static power dissipation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.