Methods and systems for reducing leakage current in semiconductor circuits
US7233197B2 · kind B2 · utility
4Cited by
18References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Dec 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Leakage currents across circuit components such as transistors are avoided by placing circuits into a low-leakage standby mode. The circuits are configured such that voltage differentials across leakage-prone circuit components are avoided when in standby mode. Various means are used to configure the circuits, such as configuration ports, data input lines, scan chains, etc. In embodiments containing reconfigurable devices, low-threshold transistors are used to implement the routing network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.