Receiver capable of correcting mismatch of time-interleaved parallel ADC and method thereof
US7233270B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 25, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Nov 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A compensation method for a receiver is disclosed, the method includes: receiving and processing an incoming signal to generate an analog input signal; utilizing a time-interleaved parallel analog-to-digital converter (ADC) for converting the analog input signal to a digital input signal according to a plurality of clock signals of different phases; equalizing the digital input signal to generate a plurality of soft decision values; generating a plurality of hard decision values according to the soft decision values; calculating a plurality of error values according to the hard decision values and the soft decision values; and compensating the receiver according to at least part of the error values.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.