Pipelined analog to digital converter with capacitor mismatch compensation
US7233276B1 · kind B1 · utility
12Cited by
5References
2Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 29, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Nov 29, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a pipelined analog to digital converter with multiple stages of sub-converters, capacitor mismatch error can be reduced by splitting the capacitors into multiple numbers and randomly selecting part of the split capacitors as feedback capacitors. The selection of feedback capacitors can be made according to a digital output, clock phase, stage number of the sub-converter or the combination thereof. The approach of the present invention can be applied to the most significant bit (MSB) stage for a pipelined ADC. Moreover, a method for implementing the same is also proposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.