Video timing display indicator
US7233349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Dec 15, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N17/00
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A timing alignment or offset display shows the relationship between a reference signal and a test signal, in particular two analog or digital video signals. Timing extraction circuits derive a lower frequency signal synchronized to horizontal lines and a higher frequency signal synchronized to the pixel sampling rate. A reference time pulse is also derived from the reference signal. Two offsets are counted by determining a line count and a sample or clock cycle count between corresponding reference points in the test and reference signals. A coarse line count offset and a fine timing offset are thereby obtained and are displayed by movable markers on opposite sides of a scale line. The markers are centering and aligned when the frame/field alignment and the color and/or sample portions of the signals correspond in time. Tabular data, distinct coloring and alarms also are depicted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.