Content addressable memory circuit with improved memory cell stability
US7233512B2 · kind B2 · utility
4Cited by
4References
26Claims
0Family size
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Key dates
| Filing date | Feb 1, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jun 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Content Addressable Memory (CAM) circuit includes memory cells preferably formed as two memory cells each having internal nodes. A compare circuit is operative with the memory cells. A common terminal (VPL) exists for the memory cells. Capacitors are added between the internal nodes of each of the memory cells and common terminal for memory cell stability.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.