Latch-based random access memory (LBRAM) with tri-state banking and contention avoidance
US7233540B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2005 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Nov 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously. Avoiding concurrent activity of the enable signals eliminates contention on the tri-state output bit lines, and thereby prevents the mutually coupled tri-state bit lines output from the first and second tri-state buffers from being active at the same time. Placing a delay between activity minimizes contention on the mutually coupled, buffered bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.