Hardware assist system and method for the timing of packets in a wireless network
US7233588B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 2002 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | May 7, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04W84/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a wireless local area network (“WLAN”), a system and method for assisting the timing calculation associated with the transmission timing of packets or data frames through the air. The present utilizes the baseband PHY processor to detect the trailing edge of the radio frequency (“RF”) packet and prevents the WLAN device from transmitting for a pre-determined amount of time. This improved system and method thereby frees the medium access controller (“MAC”) from utilizing significant microprocessor cycles for synchronization calculations and thereby increases system throughput and reduces the possibility of fast-turnaround protocol timing errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.