Packet transfer control circuit
US7233592B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2000 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Feb 17, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L12/40123
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet transfer control circuit is a part of a node in a network of nodes, in which packets of data are passed between the nodes. The packets include normal packets and write packets, and each packet includes a header portion and a data portion. The transfer control circuit includes an identification circuit which identifies if the data portion of a write packet is blank and a processor with a memory connected to the identification circuit. If the write packet is blank, as determined by the identification circuit and the processor is holding data for transmission to another node, the processor puts the data into the data portion of the packet, zero fills if the there is not enough data to fill the data portion, updates the header with the new addressee, and then passes the write packet on to the other nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.