High speed parser
US7233597B2 · kind B2 · utility
20Cited by
1References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2003 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jan 8, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/90
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed parser containing a content addressable memory (CAM) providing select values to multiplexers. The CAM is programmed to implement search rules which examine input data for specific semantics according to a protocol, and outputs the specific bit positions at which the corresponding desired data units are present. The outputs are provided to multiplexers to cause the desired data units to be selected on the corresponding output paths of the multiplexors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.