Reduced complexity efficient binarization method and/or circuit for motion vector residuals
US7233622B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2003 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Oct 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/52
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus comprising a first processing circuit and a second processing circuit. The first processing circuit may be configured to generate a motion vector residual in response to one or more macroblocks of an input signal. The second processing circuit may be configured to convert between (i) the motion vector residual and (ii) a binarized representation of the motion vector residual. The binarized representation of the motion vector residual generally comprises (i) a binarized representation of an absolute value of the motion vector residual and (ii) a binarized representation of a sign of the motion vector residual when the motion vector residual has a non-zero value. The binarized representation of the sign is generally located after an end of the binarized representation of the absolute value of the motion vector residual.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.