Method, apparatus, and computer program for evaluating noise immunity of a semiconductor device
US7233889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 23, 2002 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Sep 16, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of evaluating noise immunity of a semiconductor device is provided. An actual circuit including the semiconductor device is represented by an equivalent circuit which has a target equivalent circuit, a noise source equivalent circuit, and an external equivalent circuit connected in parallel. The target equivalent circuit represents the semiconductor device. The noise source equivalent circuit represents a noise source outside the semiconductor device, and supplies noise to the target equivalent circuit. The external equivalent circuit represents a circuit outside the semiconductor device. The noise immunity is evaluated based on a voltage or current which arises in the target equivalent circuit by the noise. In this way, the immunity of the semiconductor device against extraneous noise can be evaluated in consideration of the effects of the circuitry outside the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.