Instructions for test & set with selectively enabled cache invalidate
US7234027B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 24, 2001 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Jan 19, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0808
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for selectively enabling a cache-invalidate function supplement to a resource-synchronization instruction such as test-and-set. Some embodiments include a first processor, a first memory, at least a first cache between the first processor and the first memory, wherein the first cache caches data accessed by the first processor from the first memory, wherein the first processor executes: a resource-synchronization instruction, an instruction that enables a cache-invalidate function to be performed upon execution of the resource-synchronization instruction, and an instruction that disables the cache-invalidate function from being performed upon execution of the resource-synchronization instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.