Memory module with testing logic
US7234081B2 · kind B2 · utility
73Cited by
6References
27Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2004 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | May 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module that comprises a plurality of memory circuits, at least one serial presence detect (SPD) memory circuit, and a plurality of data lines that transfer data to and from the plurality of memory circuits. The memory module may further comprise a testing logic that utilizes data stored in the SPD memory circuit to inject a memory error into one or more of the plurality data lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.