High reliability memory module with a fault tolerant address and command bus
US7234099B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 2003 |
| Grant date | Jun 19, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high reliability dual inline memory module with a fault tolerant address and command bus for use in a server. The memory module is a card approximately 151.35 mm or 5.97 inches long provided with about a plurality of contacts of which some are redundant, a plurality of DRAMs, a phase lock loop, a 2 or 32K bit serial EE PROM and a 28 bit, a 1 to 2 register having error correction code (ECC), parity checking, a multi-byte fault reporting circuitry for reading via an independent bus, and real time error lines for determining and reporting both correctable errors and uncorrectable error conditions coupled to the server's memory interface chip and memory controller or processor such that the memory controller sends address and command information to the register via address/command lines together with check bits for error correction purposes to the ECC/Parity register. By providing the module with a fault tolerant address and command bus fault-tolerance and self-healing aspects necessary for autonomic computing systems compatible with industry-standards is realized. The memory module corrects single bit errors on the command or address bus and permits continuous memory operation indep…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.