Task concurrency management design method

US7234126B2 · kind B2 · utility

Assignees

• INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW · BE
• Katholieke Universiteit Leuven · BE
• Patras, University of · GR

Inventors

• Francky Catthoor · Temse, BE
• Peng Yang · Nanhu, CN
• Chun Wong · Leuven, BE
• Paul Marchal · Gif-sur-Yvette, FR
• Aggeliki Prayati · Athens, GR
• Nathalie Cossement · Rekkem, BE
• Rudy Lauwereins · Winksele, BE

Key dates

• Filing date: Aug 22, 2001
• Grant date: Jun 19, 2007
• Expiry date: Jun 28, 2022

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2117/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system and method of designing digital system. One aspect of the invention includes a method for designing an essentially digital system, wherein Pareto-based task concurrency optimization is performed. The method uses a system-level description of the functionality and timing of the digital system. The system-level description comprises a plurality of tasks. Task concurrency optimization is performed on said system-level description, thereby obtaining a task concurrency optimized system-level description, including Pareto-like task optimization information. The essentially digital system is designed based on said task concurrency optimized system-level description. In one embodiment of the invention, the description is includes a “grey-box” description of the essentially digital system.