Ferroelectric memory and its manufacturing method
US7235834B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 10, 2005 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Dec 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B53/30
Abstract
To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.