High-speed differential logic buffer
US7236011B2 · kind B2 · utility
4Cited by
1References
77Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 20, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Nov 21, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09432
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for a high speed digital buffer has an active load circuit connected to an output of the digital buffer. The active load circuit loads the buffer output with an active inductance to reduce the RC time constant at the buffer output. The active load circuit may be based on two active devices connected to the buffer output so as to form a differential cascode circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.