Linearizing methods and structures for amplifiers
US7236111B2 · kind B2 · utility
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17References
20Claims
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Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Feb 22, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/32
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Methods and structures are provided to enhance the linearity of amplifiers such as those which include a complementary common-collector amplifier stage. The methods and structures configure this stage so that each transistor of the stage drives an output port through a linearizing resistance. The methods and structures then control a bias current through the stage to substantially be the thermal voltage VT divided by twice the linearizing resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.