Method and program product for avoiding cache congestion by offsetting addresses while allocating memory
US7237084B2 · kind B2 · utility
2Cited by
4References
3Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 27, 2003 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Jun 4, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of allocating memory operates to avoid overlapping hot spots in cache that can ordinarily cause cache thrashing. This method includes steps of determining a spacer size, reserving a spacer block of memory from a memory pool, and allocating memory at a location following the spacer block. In an alternative embodiment, the spacer size is determined randomly in a range of allowable spacer size. In other alternative embodiments, spacers are allocated based upon size of a previously allocated memory block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.