Functional interrupt mitigation for fault tolerant computer
US7237148B2 · kind B2 · utility
Inventors
Key dates
| Filing date | Sep 8, 2003 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Oct 25, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A new method for the detection and correction of environmentally induced functional interrupts (or “hangs”) induced in computers or microprocessors caused by external sources of single event upsets (SEU) which propagate into the internal control functions, or circuits, of the microprocessor. This method is named Hardened Core (or H-Core) and is based upon the addition of an environmentally hardened circuit added into the computer system and connected to the microprocessor to provide monitoring and interrupt or reset to the microprocessor when a functional interrupt occurs. The Hardened Core method can be combined with another method for the detection and correction of single bit errors or faults induced in a computer or microprocessor caused by external sources SEUs. This method is named Time-Triple Modular Redundancy (TTMR) and is based upon the idea that very long instruction word (VLIW) style microprocessors provide externally controllable parallel computing elements which can be used to combine time redundant and spatially redundant fault error detection and correction techniques. This method is completed in a single microprocessor, which substitute for the traditional multi-pr…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.