Area optimized edge-triggered flip-flop for high-speed memory dominated design
US7237164B1 · kind B1 · utility
11Cited by
5References
53Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Nov 23, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Jun 4, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/3202
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An area optimized edge-triggered flip-flop for high-speed memory dominated design is provided. The area optimized flip-flop also provides a bypass mode. The bypass mode allows the area optimized flip-flops to act like a buffer. This allows the area optimized flip-flop to provide the basic functionality of a flip-flop during standard operation, but also allows the area optimized flip-flop to act like a buffer when desirable, such as during modes of testing of the design. The area optimized flip-flop provides most of the functionality of a typical flip-flop, while reducing the total area and power consumption of the design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.