Method for providing memory cells capable of allowing multiple variations of metal level assignments for bitlines and wordlines
US7237215B2 · kind B2 · utility
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12Claims
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Key dates
| Filing date | Oct 29, 2004 |
| Grant date | Jun 26, 2007 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for providing memory cells that allow multiple variations of metal level assignments for bitlines and wordlines is disclosed. A memory cell includes two cell elements. The first and second cell elements are identically processed up to a metal-1 layer. The first cell element is subsequently processed with bitlines on a metal-2 layer and wordlines on a metal-3 layer. Next, the second cell element is processed with bitlines on the metal-3 layer and wordlines on the metal-2 layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.