CMOS pixel with dual gate PMOS

US7238993B2 · kind B2 · utility

Assignee

• Dialog Imaging Systems Inc. · DE

Inventors

• Taner Dosluoglu · New York, US
• Nathaniel Joseph McCaffrey · Clifton, US

Key dates

• Filing date: Feb 28, 2005
• Grant date: Jul 3, 2007
• Expiry date: Jan 23, 2026

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10F39/18

Abstract

A pixel circuit with a dual gate PMOS is formed by forming two P+ regions in an N− well. The N− well is in a P− type substrate. The two P+ regions form the source and drain of a PMOS transistor. The PMOS transistors formed within the N− well will not affect the collection of the photo-generated charge as long as the source and drain potentials of the PMOS transistors are set at a lower potential than the N− well potential so that they remain reverse biased with respect to the N− well. One of the P+ regions used to form the source and drain regions can be used to reset the pixel after it has been read in preparation for the next cycle of accumulating photo-generated charge. The N− well forms a second gate for the dual gate PMOS transistor since the potential of the N− well 12 affects the conductivity of the channel of the PMOS transistor. The addition of two NMOS transistors enables the readout signal to be stored at the gate of one of the NMOS transistors thereby making a snapshot imager possible. The circuit can be expanded to form two PMOS transistors sharing a common drain in the N− well.