NAND-structured flash memory
US7239556B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 15, 2005 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Mar 9, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/5641
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A NAND-structured flash memory comprises a memory cell array wherein plural memory strings are arranged in matrix form, each of the memory cell strings including plural nonvolatile memory cells, the first conducting paths of the memory cells being connected in series, at least one of the memory cells having a function other than an external data storing function, plural first selection transistors having second conducting paths, and one end of the second conducting paths being connected to one end of the series of the first conducting paths, respectively, plural bit lines connected to the other end of the second conducting paths, plural second selection transistors having third conducting paths, and one end of the third conducting paths being connected to one end of the series of the first conducting paths, respectively, and a source line connected to the other end of the third conducting paths.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.