Dedicated processing resources for packet header generation
US7239630B1 · kind B1 · utility
20Cited by
25References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 22, 2002 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Oct 7, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L45/60
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit may include a single execution section and the L3 generation unit may include multiple parallel execution sections. When both the L2 and L3 generation units complete their operations on a particular packet, a build component combines the generated L2 and L3 information to form a complete packet header.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.