System, apparatus and method for reclaiming memory holes in memory composed of arbitrarily-sized memory devices
US7240179B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2004 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Nov 24, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0292
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system, apparatus, and method are disclosed for increasing the physical memory address space accessible to a processor, at least in part, by translating linear addresses associated with a memory hole into a subset of physical memory addresses that otherwise is inaccessible as system memory by a processor. In one embodiment, a memory controller reclaims memory holes in a system memory divided into ranges of linear addresses, where the system memory includes a number of arbitrarily-sized memory devices. The memory controller includes a memory configuration evaluator configured to determine a translated memory hole size for a memory hole, the memory hole including restricted linear addresses that translate into a subset of physical addresses. Also, memory configuration evaluator can be configured to form adjusted ranges to translate at least one linear address into a subset of physical addresses. As such, the system memory increases by at least the subset of physical addresses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.