Memory error detection reporting
US7240277B2 · kind B2 · utility
12Cited by
11References
16Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 27, 2004 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Feb 26, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system or a digital signal processor (DSP) includes single-bit-error detection hardware in its level two (L2) memory controller to mitigate the effects of soft errors. Error detection hardware detects erroneous data that is fetched by the central processing unit and signals the central processing unit. The parity is generated and checked only for whole memory line accesses. This technique is especially useful for cache memory. The central processing unit can query the memory controller as to the specific location that generated the error and decide the next course of action based on the type of data affected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.