Simulation method for semiconductor circuit device and simulator for semiconductor circuit device
US7240308B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 19, 2003 |
| Grant date | Jul 3, 2007 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A simulator and method for accurately simulating a deterioration amount and a recovery amount of transistor characteristics, by which a semiconductor device can be designed with high reliability, in which when a negative bias fate voltage is applied to a gate of the transistor, characteristics of the transistor are deteriorated. When the negative bias voltage is terminated by applying a bias free voltage, the deteriorated transistor characteristics are recovered. In a deterioration period and a recovery period, a logarithm “log(t)” is obtained for an application time “t” of the gate voltage, a deterioration amount ΔPD(t)=CD+BD·log(t) is calculated by using constants CD and BD depending on the negative bias voltage, a recovery amount ΔPR(t)=CR+BR·log(t) is calculated by using constants CR and BR depending on the bias free voltage, and the deterioration amount (ΔPD), the recovery amount (ΔPR) and a basic deterioration amount (XD) are summed up.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.