Reduced capacitance resistors
US7242074B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 2004 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Aug 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/209
Abstract
A method for reducing the parasitic capacitance in resistors, and a resistor design embodying this method are described. By creating a p-type or an n-type implant inside of an n-well or a p-substrate, respectively, where the n-well or p-substrate is located in a p-substrate or n-substrate, respectively, a capacitively coupled capacitor is formed in series connection with the parasitic inter-layer dielectric capacitance generated when the resistor is fabricated in the dielectric material. The depletion region formed thereby behaves as a series capacitor which reduces the overall capacitance of the assemblage. The n-well or p-substrate can be placed in electrical connection with a ground potential or brought to a chosen voltage to further increase the depletion region and reduce the capacitance of the resistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.