Output reporting techniques for hard intellectual property blocks
US7242217B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 2004 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Mar 23, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques for reducing the frequency of an output signal from a hard intellectual property (HIP) block on an integrated circuit are provided. By reducing the frequency of the output signal, circuit blocks in the integrated circuit that operate at a lower frequency than the HIP block are able to capture the output signal. A plurality of serially coupled flip-flops store values of an HIP output signal during each period of the output signal. Logic circuitry then generates a lower frequency HIP output signal in response to the values stored in the flip-flops. Also, a flip-flop can generate a heartbeat signal that is used to determine whether a signal within an HIP block is operating properly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.