Microprocessor with power saving clock
US7242230B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2004 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jul 1, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.