Method and arrangement for testing a power output stage
US7242244B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2004 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Sep 16, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/40
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An arrangement for testing a power output stage, with the power output stage includes at least one half bridge with an upper semiconductor switch and a lower semiconductor switch connected in series and to which an operating voltage is applied. A junction point between the semiconductor switches of the at least one half bridge forms an output. A control device performs a test to determine whether the voltage at the output is within a predetermined central tolerance band when the semiconductor switches are not switched on, a test to determine whether the voltage at the output is within a predetermined upper tolerance band when the upper semiconductor switch is switched on, and a test to determine whether the voltage at the output is within a predetermined lower tolerance band when the lower semiconductor switch is switched on. The power output stage is identified as being sound when all of the output voltages are within the respective tolerance bands.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.