Self-analyzing memory word
US7242599B2 · kind B2 · utility
Inventor
Key dates
| Filing date | Apr 22, 2005 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | May 13, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content-addressable memory stores a plurality of words, each word with intrinsic capability: Global bus-1 selects a set of bits in each word. Global bus-2 selects a disjoint set of bits in each word. Circuits approximately adiabatic in each word, toggle bus-2 bits if and only if all bus-1 bits are true. Toggling selectively, as above, will copy selected bits to new locations, and will calculate a given Boolean function on a given subset of bits. Each word, in parallel with other words, can thus accomplish any task that can be composed of bit-copying and Boolean operations. Every word systematically undergoes modification during each processing step without reading or writing to a global bus. This avoids an increase in processing time and loss of efficiency for global bus operations. Self-analyzing memory words support a programmable computer, massively parallel, logically reversible and approximately adiabatic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.