Memory device with reduced leakage current
US7242630B2 · kind B2 · utility
2Cited by
3References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2005 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Dec 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C5/147
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for reducing the bitline leakage current while maintaining a level of performance characteristics of low threshold voltage transistors in deep submicron CMOS technology incorporates a reference voltage generator circuit in combination with bias transistor MBIAS. The output of a static logic gate is connected to the input terminal of the pull-down devices. The reduction in leakage current through pull-down devices whenever a read operation is not performed contributes to a significant reduction in overall leakage current in the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.