Memory device, memory managing method and program
US7242632B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 17, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Feb 2, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0246
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device, performs fast data renewal and erasure, and is not easily degraded. In the memory area of a flash memory, each block is divided into physical pages and each physical pages is divided into logical pages. A redundancy portion is provided for each physical page. When supplied with to-be-written data and the logical address of a write destination, a CPU writes this data in an empty logical page and allocates the supplied logical address to this logical page. An old data flag in the redundancy portion in that physical page which includes a logical page having old data stored therein is changed in such a way as to indicate that data in this logical page is invalid. New data writing is done in that logical page to which a logical address is not allocated. At the time of flash-erasing a block, data which is stored in that logical page which is indicated by the old data flag is not transferred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.