Decision feedback equalizer (DFE) for jitter reduction
US7242712B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 8, 2005 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Sep 3, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03057
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A decision feedback equalizer (DFE) for a receiver that can reduce jitter is disclosed. The DFE uses an equalizer structure that employs a symbol sampling operation at a decision device, also known as a slicer. In a receiver, the phase of a signal, such as an equalized signal, is typically estimated from zero crossings in the clock recovery operation. Fluctuations in these zero crossings makes phase of the reproduced clock unstable, which decreases error performance in an associated receiver. Embodiments advantageously align inter-symbol interference (ISI) canceling terms from a feedback filter (FBF) relatively well, and thereby provide equalization of a relatively large portion of a symbol period. This advantageously stabilizes the phase of an equalized signal and reduces jitter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.