Digital phase-locked loop with master-slave modes
US7242740B2 · kind B2 · utility
10Cited by
7References
26Claims
0Family size
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Key dates
| Filing date | Apr 16, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Mar 11, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital phase locked loop (DPLL) for providing clock synchronization in backplane bus systems has a loop filter with selectable high and low bandwidth modes. The DPLL is thus capable of respectively attenuating or tracking jitter from an input reference clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.