Maintaining packet order using hash-based linked-list queues
US7243184B1 · kind B1 · utility
13Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 12, 2002 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Oct 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Ordering logic ensures that data items being processed by a number of parallel processing units are unloaded from the processing units in the original per-flow order that the data items were loaded into the parallel processing units. The ordering logic includes a pointer memory, a tail vector, and a head vector. Through these three elements, the ordering logic keeps track of a number of “virtual queues” corresponding to the data flows. A round robin arbiter unloads data items from the processing units only when a data item is at the head of its virtual queue.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.