Cache memory architecture with system controller device that compares cache tags to memory addresses received from microprocessor
US7243192B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 2006 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Jun 27, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.