Low power memory controller that is adaptable to either double data rate DRAM or single data rate synchronous DRAM circuits
US7243254B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 5, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Mar 14, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1694
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller is provided and a method for transferring data between the memory controller and a memory device. The memory controller can be implemented on an integrated circuit that also contains an execution unit. The execution unit can be clocked at a first clock rate, whereas the memory controller can be selectively clocked at either the first clock rate or a second clock rate that is approximately one-half frequency of the first clock rate. By clocking the memory controller at either the first clock rate or the second clock rate, the memory controller can accommodate different types of semiconductor memory. For example, the memory controller can control single data rate (SDR) DRAM memory if it is clocked at a first clock rate. Conversely, the memory controller can control double data rate (DDR) DRAM memory if it is clocked at approximately one-half the first clock rate. By selectively clocking the memory controller at different clocking rates, the memory controller need not be modified in hardware, yet can accommodate different memory devices by allowing a user to simply plug one type of memory into a receptacle rather than another depending on the cost constraints and u…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.