System and method for reducing the size of RC circuits
US7243313B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2003 |
| Grant date | Jul 10, 2007 |
| Priority date | — |
| Expiry date | Dec 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of transforming a first topology to a reduced topology is disclosed. One preferred embodiment of the present invention includes a method of transforming a circuit from a first topology to a reduced topology, said first topology comprising a plurality of inter-connected circuit elements. The method comprises the steps of: (a) identifying one or more circuit elements; (b) analyzing the effect of reducing one or more of said identified circuit elements on the topological and physical characteristics of said circuit; and (c) if the effect satisfies a first standard, generating a second topology reflecting the reduction of one or more identified circuit elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.