System for reducing noise induced from reference plane currents
US7245506B2 · kind B2 · utility
1Cited by
14References
16Claims
0Family size
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Key dates
| Filing date | Jan 8, 2004 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Oct 3, 2024 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method of reducing noise induced from reference plane currents is disclosed. The method includes routing a first path for an electrical trace on a circuit board such that the first path references a voltage plane. The method further includes routing a second path for the electrical trace on the circuit board such that the second path references a ground plane whereby the second path is substantially similar to the first path. The method further includes electrically coupling the first path to the second path at each of the ends of the first and second paths such that noise induced into the electrical trace is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.