Multi-link protocol reassembly assist in a parallel 1-D systolic array system
US7245615B1 · kind B1 · utility
7Cited by
4References
29Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2001 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Aug 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/168
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention comprises a technique for performing a reassembly assist function that enables a processor to perform packet reassembly in a deterministic manner. The technique employed by the present invention enables a processor to reassemble a packet without having to extend its normal processing time to reassemble a varying number of fragments into a packet. The invention takes advantage of the fact that the reassembly assist can be dedicated exclusively to reassembling a packet from a series of fragments and thereby offloading the reassembly process from the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.