System and methods of recovering a clock from NRZ data
US7245683B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Apr 11, 2003 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | May 25, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A substantially passive implementation of a clock recovery circuit may be employed to reduce or eliminate the amount of jitter added to the recovered clock by the recovery circuitry. NRZ data may be received in differential form (i.e., a separate NRZ signal and an inverted NRZ signal are received). The inverted NRZ data may be delayed by one-half of a unit interval with respect to the NRZ data by a delay element. The NRZ data and the delayed NRZ data may be combined by a broadband combiner (e.g., a resistive adder). The combined signal may be split into two signals. The two split signals may be rectified by suitable components. One of the limited split signals may be subtracted from the other limited split signal to generate an output signal. The generated output signal then possesses a spectral component at a clock frequency of the NRZ data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.