Digital phase-locked loop device for synchronizing signal and method for generating stable synchronous signal
US7245687B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2003 |
| Grant date | Jul 17, 2007 |
| Priority date | — |
| Expiry date | Jun 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/50
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) device is disclosed. The PLL device includes an interpolator receiving and processing an input signal by an interpolation operation in response to an interpolation timing value to obtain an output signal, a timing error detector in communication with the interpolator for detecting a timing error value of the output signal, a loop filter in communication with the timing error detector for outputting the interpolation timing value to the interpolator in response to the timing error value, and a lock controller in communication with the loop filter for adjusting the interpolation timing value according to a timing quality of the output signal, and providing the adjusted interpolation timing value for the interpolator. A signal generation method for use in the data pick-up device with the aid of the digital phase-locked loop (PLL) device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.